Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic

Low-Voltage MOS Current Mode Logic Multiplexer

In this paper, a new low-voltage MOS current mode logic (MCML) multiplexer based on the triple-tail cell concept is proposed. An analytical model for static parameters is formulated and is applied to develop a design approach for the proposed low-voltage MCML multiplexer. The delay of the proposed low-voltage MCML multiplexer is expressed in terms of the bias current and the voltage swing so th...

Jitter Analysis of Current-Mode Logic Frequency Dividers

Design and Analysis of Low-Voltage Current-Mode Logic Buffers

This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The differential architecture of a CML buffer makes it functionally robust in the presence of environmental noise sources (e.g., crosstalk, power/ground noise). The circuit design ...

An Analysis of MOS Current Mode Logic for Low Power and High Performance Digital Logic

In this work, MOS Current Mode Logic (MCML) is analyzed for application to low power, mixed signal environments. A small MCML cell library is developed and optimized for several different performance requirements. The cells are then applied to the generation of ripple adders and piplelined CORDIC structures and compared with equivalent CMOS circuits. MCML CORDICs are designed which can operate ...

Design of A Low - Voltage and Low - Power Voltage Mode

A low-voltage and low-power voltage mode adder/subtractor using MOSFETs in weakinversion is presented in this paper. Since the MOSFETs in the proposed circuit are biased in weak inversion, consequently its power dissipation is very low. The proposed circuit has been simulated with the HSPICE using a N-well 0.35μm 2p4m process and the results show that, under the supply voltage of 1V, the power ...